1. Field of the Invention
The present invention relates to a read only memory, and more particularly, to an optically controlled read only memory that is capable of generating specific program code after being illuminated by light.
2. Description of the Prior Art
Read only memory (ROM) is a form of semiconductor memory, which is commonly utilized in electronic computing systems that do not require frequent data alteration, in which file folders of this kind of system would not be erased as the power is being turned off. Applications of this type of system also include basic input output system (BIOS) for personal computers, other micro-computing systems, portable electronic products, home appliances, or firmware within toys.
Commercial read only memories today are roughly divided into following four categories: 1) Programmable Read Only Memory (PROM); 2) Erasable Programmable Read Only Memory (EPROM); 3) One Time Programmable Read Only Memory (OTPROM); and 4) Electrically Erasable Programmable Read Only Memory (EEPROM). PROM includes determinant fuses that can be cut off by electrical current (by the user) for writing required data or program. However, as a burn is made, it cannot be altered. EPROM is typically programmed by using high voltage and erased by exposure of ultraviolet light. As the data is erased, the ROM can be reused again. A quartz window is commonly formed on the package housing of EPROM for exposure purpose. The writing mechanism of OTPROM is similar to that of EPROM. However in order to reduce cost, codes being programmed is not erased, thus no window is being formed in this type of memory. The operation of EEPROM is similar to that of EPROM. However, the erasing method for this type of memory is achieved by high electrical field, thus no window is required.
Depending on the operation including read, erase, and program of a memory, the structure and fabrication process for each read only memory also differs accordingly. An example of a read only memory is disclosed in U.S. Pat. No. 5,959,877. Referring to FIG. 1, FIG. 1 illustrates a structural view of a read only memory according to the prior art. As shown in FIG. 1, the read only memory is fabricated on a substrate 1, in which the substrate 1 includes a plurality of n-type doping regions 2-1, 2-2, 2-3, 2-4, 2-5, 2-6, a plurality of insulating films 3-1, 3-2, 3-3, 3-4, 3-5, and a plurality of polysilicon films 4-1, 4-2, 4-3, 4-4, 4-5 disposed on the insulating films. Preferably, the polysilicon films, the insulating films disposed under the polysilicon films, and the n-type doping regions formed at two sides of the above films are used to define a plurality of n-channel MOS transistor (hereinafter would be referred to as NMOS transistors). Each of the polysilicon film, serving as the gate of the NMOS transistor is electrically connected to corresponding word lines, and the n-type doping regions are the source/drain of the NMOS transistor. The read only memory also includes a first metal wiring layer 5-1, 5-2, 5-3, 5-4, 5-5, 5-6 and a second metal wiring layer 6-1, 6-2, 6-3, 6-4, 6-5, 6-6. A plurality of via plugs 10-1, 10-2, 10-5, 10-6 are disposed between a portion of the first metal wiring layer and the second metal wiring layer, and the first wiring layer 5-1, 5-2, 5-3, 5-4, 5-5, 5-6 is electrically connected to the n-type doping regions 2-1, 2-2, 2-3, 2-4, 2-5, 2-6 through the via plugs.
The second metal wiring layer 6-2, 6-3, 6-4, 6-5 preferably serving as the bit line BL0, BL1, BL2, BL3 of the read only memory, and the intersecting region of the word lines and the bit lines is a memory cell for storing data, in which the bit lines BL0, BL1 are electrically connected to the n-type doping region 2-2, 2-5 through the via plug 10-2, 10-5. While the read only memory is fabricated, the presence of the via plug disposed between the first metal wiring layer and the second metal wiring layer would determine the message data stored in the memory cell to be either “0” or “1”, thereby constituting the program code of the read only memory. Therefore, voltage comes from the bit line would turn on the NMOS transistor through the connected gate and at the same time apply a precharge potential while the data stored in the read only memory is read. As the via plugs 10-2, 10-5 are electrically connected to the second metal wiring layer 6-2, 6-5, the first metal wiring layer 5-2, 5-5, and the n-type doping regions 2-2, 2-5, and causing the potential of the bit lines BL0 and BL3 to be lower than the precharge potential, such as a ground potential, the bit lines BL1 and BL2 maintained at precharge potential would read data stored in the memory cell as “0”, whereas the bit lines BL0 and BL3 below the precharge potential would read data stored in the memory cell as “1”.
It is evident that the conventional read only memories not only come with a unique structure and fabricate with great complexity, in which the program code embedded therein is fundamentally decided during wafer fabrication stage. Moreover, certain operation procedure is required to write required data or firmware into the memory, and only one single program code is stored into the memory at a time. The conventional read only memory undoubtedly causes great inconvenience and carries virtually no variability.